Clock
Local bus lock programmable uo to 66MHz for transfer beetween PCI bridge and user FPGA.
High performance user clock programmable up to 500 MHz. Additional 200MHz reference for IOB delay circuits.
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Rear I/O
64 Single-ended or 32 Differential signal on PMC Pn4 connector 3.3V or 2.5V prgrammavle voltage levels.
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Software Support
Driver for WinNT, 2000, Xp and VxWorks
Api whit template designe in VHDL and Veerilog
Library for Simulink/system Generator firmware developmet
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For more specific details download Here ....

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